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Espressif Systems /ESP32 /RMT /INT_CLR

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Interpret as INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH2_TX_END)CH2_TX_END 0 (CH1_RX_END)CH1_RX_END 0 (CH5_ERR)CH5_ERR 0 (CH6_TX_THR_EVENT)CH6_TX_THR_EVENT

Fields

CH3_TX_END

Set this bit to clear the rmt_ch3_rx_end_int_raw…
CH7_TX_END

Set this bit to clear the rmt_ch7_rx_end_int_raw…
CH6_TX_END

Set this bit to clear the rmt_ch6_rx_end_int_raw…
CH1_TX_END

Set this bit to clear the rmt_ch1_rx_end_int_raw…
CH4_TX_END

Set this bit to clear the rmt_ch4_rx_end_int_raw…
CH5_TX_END

Set this bit to clear the rmt_ch5_rx_end_int_raw…
CH0_TX_END

Set this bit to clear the rmt_ch0_rx_end_int_raw…
CH2_TX_END

Set this bit to clear the rmt_ch2_rx_end_int_raw…
CH2_RX_END

Set this bit to clear the rmt_ch2_tx_end_int_raw.
CH6_RX_END

Set this bit to clear the rmt_ch6_tx_end_int_raw.
CH7_RX_END

Set this bit to clear the rmt_ch7_tx_end_int_raw.
CH0_RX_END

Set this bit to clear the rmt_ch0_tx_end_int_raw.
CH4_RX_END

Set this bit to clear the rmt_ch4_tx_end_int_raw.
CH5_RX_END

Set this bit to clear the rmt_ch5_tx_end_int_raw.
CH3_RX_END

Set this bit to clear the rmt_ch3_tx_end_int_raw.
CH1_RX_END

Set this bit to clear the rmt_ch1_tx_end_int_raw.
CH1_ERR

Set this bit to clear the rmt_ch1_err_int_raw.
CH7_ERR

Set this bit to clear the rmt_ch7_err_int_raw.
CH2_ERR

Set this bit to clear the rmt_ch2_err_int_raw.
CH6_ERR

Set this bit to clear the rmt_ch6_err_int_raw.
CH0_ERR

Set this bit to clear the rmt_ch0_err_int_raw.
CH4_ERR

Set this bit to clear the rmt_ch4_err_int_raw.
CH3_ERR

Set this bit to clear the rmt_ch3_err_int_raw.
CH5_ERR

Set this bit to clear the rmt_ch5_err_int_raw.
CH7_TX_THR_EVENT

Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.
CH5_TX_THR_EVENT

Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.
CH4_TX_THR_EVENT

Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.
CH0_TX_THR_EVENT

Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.
CH2_TX_THR_EVENT

Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.
CH3_TX_THR_EVENT

Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.
CH1_TX_THR_EVENT

Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.
CH6_TX_THR_EVENT

Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data